By Topic

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Subho Chatterjee ; Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta , GA, USA ; Sayeef Salahuddin ; Saibal Mukhopadhyay

This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 3 )