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Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

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4 Author(s)
Heng-Ming Hsu ; Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan ; Jhao-Siang Huang ; Szu-Yuan Chen ; Szu-Han Lai

This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-??m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and ??0.5?? with a chip outer dimension of 100 ??m .

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Microwave Theory and Techniques, IEEE Transactions on  (Volume:58 ,  Issue: 4 )