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Soft-decision-based forward error correction (FEC) and its practical implementation for 100 Gb/s transport systems are discussed. In applying soft-decision FEC to a digital coherent transponder, we address the configuration of the frame structure of the FEC. For dual-polarized multilevel modulation formats, the keys are having the FEC frames constructed individually for each polarization and a multilane distribution architecture to align each frame. We present two types of soft-decision FEC. One is the concatenation of a Reed-Solomon code and a low-density parity-check (LDPC) code with 2-bit soft decision yielding a Q limit of 7.5 dB. The other, even more powerful, is a triple-concatenated FEC, with a pair of concatenated hard-decision-based block codes further concatenated with a soft-decision-based LDPC code for 20.5% redundancy. We expect that the proposed triple-concatenated codes can achieve a Q limit of 6.4 dB and a net coding gain of 10.8 dB at a post-FEC bit error ratio of 10-15. For the practical implementation of soft-decision FEC for 100 Gb/s systems, we developed field-programmable gate array boards to emulate it. The concept of hardware emulation, with a scalable architecture for the FEC decoder boards, is introduced by way of a pipelined architecture.