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Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS

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5 Author(s)
S. -H. Cho ; KAIST, 119-Mujiro, Yuseong-gu, Daejeon 305-732, Republic of Korea ; H. -D. Lee ; K. -D. Kim ; S. -T. Ryu
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A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of 107 and 109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 5 )