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FPGA leakage power reduction using clb-clustering technique

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2 Author(s)
Tohidi, M.M. ; Sch. of ECE, Univ. of Tehran, Tehran, Iran ; Masoumi, N.

FPGAs with supply voltage programmability have been proposed recently to reduce FPGA power. In this paper, we propose CLB-clustering design technique that employs VDD programmable and power gating methods to reduce leakage in standby mode. Compared to the conventional VDD-programmable architecture, our architecture reduces the leakage power by - 32.78 dB with 2.32% more area.

Published in:

Nanoelectronics Conference (INEC), 2010 3rd International

Date of Conference:

3-8 Jan. 2010