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Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

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14 Author(s)
Hutin, L. ; LETI, CEA, Grenoble, France ; Vinet, M. ; Poiroux, T. ; Le Royer, C.
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We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20 nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22 nm nodes. We demonstrate pFET devices with promising electrical behavior (ION = 790 ¿A/¿m; IOFF = 60 nA/¿m @ VDS = -1.2 V; Lg = 30 nm), suitable for high performance applications. Excellent SCE control is also reported down to 30 nm (DIBL = 50 mV/V), through the use of Double Gate transistors.

Published in:

Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference:

7-9 Dec. 2009