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A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

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9 Author(s)
Ta-Chuan Liao ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Sheng-Kai Chen ; Yu, M.H. ; Wu, Chun-Yu
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A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Published in:

Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference:

7-9 Dec. 2009