A 0.5V operation, 32% lower active power, 42% lower leakage current, ferroelectric 6T-SRAM with VTH self-adjusting function for 60% larger St atic Noise Margin

A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The proposed SRAM has a unique configuration to apply the body of NMOS and PMOS with V_DD and V_SS. During the read and the hold, the V_TH of Fe-FETs automatically changes to increase the static noise margin, SNM, by 60%. During the sand-by, the V_TH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the V_TH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the V_TH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the V_DD reduction by 0.11 V, which decreases the active power, f × C × V_DD ², by 32%. Since the transistor count is minimized to 6 which is similar to the conventional SRAM, the proposed SRAM realizes the smallest area.