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A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The proposed SRAM has a unique configuration to apply the body of NMOS and PMOS with VDD and VSS. During the read and the hold, the VTH of Fe-FETs automatically changes to increase the static noise margin, SNM, by 60%. During the sand-by, the VTH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the VTH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the VTH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the VDD reduction by 0.11 V, which decreases the active power, f Ã C Ã VDD 2, by 32%. Since the transistor count is minimized to 6 which is similar to the conventional SRAM, the proposed SRAM realizes the smallest area.
Electron Devices Meeting (IEDM), 2009 IEEE International
Date of Conference: 7-9 Dec. 2009