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Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method

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9 Author(s)
Fukushima, T. ; Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan ; Iwata, E. ; Ohara, Y. ; Noriki, A.
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We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 ¿m and 10 ¿m were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200°C without applying mechanical pressure. In both of the self-assembly-based 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbump-to-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers.

Published in:

Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference:

7-9 Dec. 2009

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