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Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

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18 Author(s)
D. Y. Chen ; Integrated Interconnect and Packaging Division, R&D, Taiwan Semiconductor Manufacturing Company Ltd., No. 8, Li-Hsin Rd.6, Hsin-Chu Science Park, Taiwan, R.O.C. ; W. C. Chiou ; M. F. Chen ; T. D. Wang
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High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300 mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.

Published in:

2009 IEEE International Electron Devices Meeting (IEDM)

Date of Conference:

7-9 Dec. 2009