By Topic

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)
Kim, Y.S. ; Fujitsu Microelectron. Ltd., Mie, Japan ; Tsukune, A. ; Maeda, N. ; Kitada, H.
more authors

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

Published in:

Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference:

7-9 Dec. 2009