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Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

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4 Author(s)
Raychowdhury, A. ; Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA ; Somasekhar, D. ; Karnik, T. ; De, V.

This paper presents modeling and analysis of 1T-1MTJ STT RAM memory arrays under process variations and thermal disturbances. Bounds on the magnetic material design space for embedded applications are illustrated. Impact of relaxed timing/area and the effect of scaling for 1T-1MTJ bitcells have been evaluated.

Published in:
Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference: 7-9 Dec. 2009

Page(s):
1 - 4
E-ISBN :
978-1-4244-5640-6
Print ISBN:
978-1-4244-5639-0
INSPEC Accession Number:
11207357
Conference Location :
Baltimore, MD
Digital Object Identifier :
10.1109/IEDM.2009.5424242
Product Type:
Conference Publications

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