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This paper presents modeling and analysis of 1T-1MTJ STT RAM memory arrays under process variations and thermal disturbances. Bounds on the magnetic material design space for embedded applications are illustrated. Impact of relaxed timing/area and the effect of scaling for 1T-1MTJ bitcells have been evaluated.
Electron Devices Meeting (IEDM), 2009 IEEE International
Date of Conference: 7-9 Dec. 2009