A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM

This paper presents an ultra-low-power singlechip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 × 1.7 mm
²
in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34 ¿W under a network environment.