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We present several issues for the design of a UHF-band near-field RFID tag chip. The power management of the analog block includes voltage multiplier, RF limiter, and regulator. The signal processing part includes ASK modem, clock generator, low voltage detector, analog random number generator, and power-on-reset. The digital control for the tag chip is based on the EPCglobal Gen-2 protocol. Analog block includes a high dynamic range regulator with no voltage drop limiter. The tag chip was implemented using Hynix 0.18 Â¿m CMOS process. The tag chip includes 4kb EEPROM to store relative large information needed for security function. The chip size synthesized using 6 metal process was about 1 Ã 1 mm2.