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3D graphics cache system to maximize memory utilization for an embedded system

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4 Author(s)
Youngjin Chung ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Kilwhan Lee ; Jinaeon Lee ; Yongsurk Lee

In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopting a new write back algorithm and the texture cache also enhances the performance by adopting a multi-level, multi-port and non-blocking architecture. And all caches are optimized for AMBA3.0 AXI on-chip bus protocol. Also the proposed cache architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses and improving cache efficiency by implementing novel cache architectures and multiple outstanding transactions. Also we can reduce a peak power which is a critical problem for an embedded system. We have evaluated the new proposed caches on 3D graphics IP on a SOC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed methods.

Published in:

SoC Design Conference (ISOCC), 2009 International

Date of Conference:

22-24 Nov. 2009