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An Advanced BIRA using parallel sub-analyzers for embedded memories

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3 Author(s)
Woosik Jeong ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Taewoo Han ; Sungho Kang

Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.

Published in:

SoC Design Conference (ISOCC), 2009 International

Date of Conference:

22-24 Nov. 2009

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