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Low-power video encoder/decoder chip set for digital VCRs

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9 Author(s)
Hasegawa, K. ; Semicond. Res. Office, Panasonic Technol., Palo Alto, CA, USA ; Ohara, K. ; Oka, A. ; Kamada, T.
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This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm2 and 79 mm2 die, respectively

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 11 )