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A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

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13 Author(s)
Kuroda, T. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Fujita, T. ; Mita, S. ; Nagamatsu, T.
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A 4 mm2, two-dimensional (2-D) 8×8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V DD-Vth design space is also studied

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 11 )