Referenced Items are not available for this document.
A 4 mm2, two-dimensional (2-D) 8×8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V DD-Vth design space is also studied
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:31
,
Issue:
11
)
Date of Publication: Nov 1996
- Page(s):
- 1770 - 1779
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5433400
- Digital Object Identifier :
- 10.1109/JSSC.1996.542322
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1996
- Sponsored by :
- IEEE Solid-State Circuits Society
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