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A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

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4 Author(s)
von Kaenel, V. ; Swiss Center for Electron. & Microtechnol. Inc., Neuchatel, Switzerland ; Aebischer, D. ; Piguet, C. ; Dijkstra, E.

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 11 )