Referenced Items are not available for this document.
A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:31
,
Issue:
11
)
Date of Publication: Nov 1996
- Page(s):
- 1618 - 1624
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5427508
- Digital Object Identifier :
- 10.1109/JSSC.1996.542306
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1996
- Sponsored by :
- IEEE Solid-State Circuits Society
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