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Scalable transformer model based on ladder topological equivalent circuit for Si RFICs

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4 Author(s)
Shiramizu, N. ; Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan ; Masuda, T. ; Nakamura, T. ; Washio, K.

Scalable modeling methodology of on-chip spiral interleaved transformer is proposed. The novel equivalent circuit based on ladder topology is composed of lumped elements and their parameters are completely derived from the physical structure. The circuit topology enables to express the inductive and capacitive coupling effect between half turn segmented wires accurately. The circuit also contributes to obtain the scalability related to wire width/space, length, and diameter. In this model, coupling capacitance between adjacent wires is given by considering parallel paths through oxide layer and Si substrate. The model simulation result matched the measurement result of a fabricated transformer TEG with the error less than 5% for wide frequency range up-to quasi-millimeter wave band.

Published in:

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on

Date of Conference:

11-13 Jan. 2010