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Simple and quick turnaround time fabrication process for deep submicrometer CMOS generation

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4 Author(s)
Koike, H. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Matsuoka, F. ; Ohtsuka, H. ; Kakumu, M.

Process simplification and turnaround time reduction for deep submicrometer CMOS fabrication are discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation processes are extracted as items for process simplification. A combination of shallow trench isolation with retrograde well structure and single mask step well/gate doping technique is proposed for deep submicrometer CMOS fabrication. This simplified CMOS process can achieve a reduction of five mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, a 10% process step reduction and a 20% manufacturing turnaround time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:9 ,  Issue: 4 )