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Identifying redundancies using reduced symbolic simulation [digital VLSI circuits]

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2 Author(s)
B. Mathew ; MIPS Technol. Inc., Silicon Graphics Comput. Syst., Mountain View, CA, USA ; D. G. Saab

Redundancies are introduced in digital VLSI circuits due to immature synthesis techniques. Test generation algorithms have problems in handling them as well. Redundancy identification becomes important as a result. This paper presents a redundancy identification algorithm that does not rely on branch-and-bound search techniques. It utilizes a reduced form of symbolic simulation and contains several new techniques to aid in this process. Results are presented on the ISCAS circuits

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:4 )

Date of Conference:

12-15 May 1996