Identifying redundancies using reduced symbolic simulation [digital VLSI circuits]

Redundancies are introduced in digital VLSI circuits due to immature synthesis techniques. Test generation algorithms have problems in handling them as well. Redundancy identification becomes important as a result. This paper presents a redundancy identification algorithm that does not rely on branch-and-bound search techniques. It utilizes a reduced form of symbolic simulation and contains several new techniques to aid in this process. Results are presented on the ISCAS circuits.