High-level data conversion synthesis by symbolic methods

A new symbolic method for high-level synthesis of data conversion systems is described. This consists of translating the formal HDL description of a data conversion algorithm into a graph representation containing both analog and digital data, and then carrying out highly efficient symbolic manipulations to generate the circuit topology. A set of symbolic graph simplifying rules, for graph compaction into a canonical form, together with functional block pattern recognition techniques offer a considerable reduction of the search space and thus allow the overall synthesis process to be completed within very short computation times. The effectiveness of the proposed method is illustrated for the synthesis of data conversion systems implementing the well known successive approximation, flash, two-step flash and pipeline algorithms. Besides, it is also shown how the proposed method can be employed for the exploration of a wider range of data conversion topologies implementing innovative conversion algorithms.