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Timing optimization algorithm for design of high performance VLSI systems

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2 Author(s)
Taegyu Lee ; Sch. of Comput., SoongSil Univ., Seoul, South Korea ; Hoon Chung

In designing VLSI systems, need for high performance and reliability is becoming an important issue. This paper provides an algorithm which can achieve high performance and reliability by optimizing delays of components to satisfy the timing constraints. A unified algorithm which executes optimization by adjusting the path delays of circuits in a more efficient way within reasonable computer time and memory requirements. Experimental result shows the efficiency of the proposed algorithm

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:4 )

Date of Conference:

12-15 May 1996