Algorithms for optimal introduction of redundant logic for timing and area optimization

In this paper we study algorithms for systematically introducing redundant into a circuit for timing and formulations of the optimization problem. First we study a logic-level versions of the problem and show that they are NP-hard, but not in the strong sense. We then propose pseudo-polynomial algorithms for these problems. Second, we introduce a layout level problem formulation in which selection of fanout trees is constrained by physical locations of sink pins. For this version of the problem we formalize this constraint by imposing a sink ordering and propose an efficient algorithm based on shortest paths computations in a directed graph derived from the problem instance.