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Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter (ADC). At the circuit-level, device-types and supply-voltages are jointly optimized for the residue amplifier of a pipeline stage to minimize power. At the architecture-level, the nonlinearity contribution from stage gain error is optimally distributed to further minimize combined power dissipation. The optimizations take advantage of an analytical optimization method based on geometric programming for a quantitative tradeoff analysis. All of the proposed power optimizations are applied to the design of a two-way interleaved 8-bit 320 MS/s pipelined ADC in 90-nm CMOS technology. Measured performance from a prototype chip shows 7.30-bit of ENOB at Nyquist input frequency with DNL of -0.35/+0.45 LSB and INL of -0.72/+0.89 LSB, while dissipating 12.77 mW from 2.1 V/1.2 V supplies. The achieved conversion efficiency is 253fJ/conv-step.