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Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies

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3 Author(s)
Alioto, M. ; Dipt. di Ing. dell''Inf. (DII), Univ. di Siena, Siena, Italy ; Consoli, E. ; Palumbo, G.

In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 5 )