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A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

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6 Author(s)
J. Singh ; Department of Computer Science, University of Bristol, UK ; K. Ramakrishnan ; S. Mookerjea ; S. Datta
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Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6 T SRAM cells. To overcome this limitation, 7 T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6 T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6 T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7 T TFET SRAM cell. We achieve a leakage reduction improvement of 700 X and 1600 X over traditional CMOS SRAM designs at VDD of 0.3 V and 0.5 V respectively which makes it suitable for use at ultra-low power applications.

Published in:

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

Date of Conference:

18-21 Jan. 2010