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Built-in self at-speed Delay Binning And Calibration Mechanism in wireless test platform

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3 Author(s)
Chen-I Chung ; Dept. of Electron. Eng., Feng-Chia Univ., Taichung, Taiwan ; Jyun-Sian Jhou ; Ching-Hwa Cheng

An at-speed BIST delay testing technique is proposed. It differs from traditional circuit speed testing techniques by changing the system clock rate. This method supplies test pattern to the circuit using lower-speed clock frequency, then applies internal BIST circuit to adjust clock edge for circuit at-speed delay testing and speed binning. The self wide-range (26%~76%), fine-scale (34 ps) duty cycle adjustment technique with high-precision (28 ps) calibration circuit is proposed for at-speed delay test and performance binning. The contribution of this work is the proposal of a feasible self at-speed delay testing technique. Test chip DFT strategies are fully validated by instruments and HOY wireless test system.

Published in:

Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific

Date of Conference:

18-21 Jan. 2010