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In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90 nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.
Date of Conference: 18-21 Jan. 2010