Referenced Items are not available for this document.
In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90 nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.
Published in:
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Date of Conference: 18-21 Jan. 2010
- Page(s):
- 373 - 374
- E-ISBN :
- 978-1-4244-5767-0
- Print ISBN:
- 978-1-4244-5765-6
- INSPEC Accession Number:
- 11153834
- Conference Location :
- Taipei
- Digital Object Identifier :
- 10.1109/ASPDAC.2010.5419855
- Product Type:
- Conference Publications
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