By Topic

Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Naoto Miyamoto ; New Industry Creation Hatchery Center, Tohoku University, Sendai, Miyagi 980-8579, Japan ; Tadahiro Ohmi

In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90 nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.

Published in:

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

Date of Conference:

18-21 Jan. 2010