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MuCCRA-3: A low power dynamically Reconfigurable Processor Array

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7 Author(s)
Saito, Y. ; Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan ; Sano, T. ; Kato, M. ; Tunbunheng, V.
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MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC (System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. DRPAs including MuCCRA-3 provide multiple sets of configuration data called hardware contexts, and switch them in a clock cycle. For low power computation, the PE array structure of MuCCRA-3 is optimized according to the evaluation results of previous prototypes, MuCCRA-1 and 2, and was implemented with 65 nm low power CMOS process from Fujitsu. By using a real chip, the power consumption and performance are evaluated. The evaluation results suggest that MuCCRA-3 works with extremely low power: 10 mW-13 mW.

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Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific

Date of Conference:

18-21 Jan. 2010

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