By Topic

MuCCRA-3: A low power dynamically Reconfigurable Processor Array

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Saito, Y. ; Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan ; Sano, T. ; Kato, M. ; Tunbunheng, V.
more authors

MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC (System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. DRPAs including MuCCRA-3 provide multiple sets of configuration data called hardware contexts, and switch them in a clock cycle. For low power computation, the PE array structure of MuCCRA-3 is optimized according to the evaluation results of previous prototypes, MuCCRA-1 and 2, and was implemented with 65 nm low power CMOS process from Fujitsu. By using a real chip, the power consumption and performance are evaluated. The evaluation results suggest that MuCCRA-3 works with extremely low power: 10 mW-13 mW.

Published in:

Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific

Date of Conference:

18-21 Jan. 2010