Modeling and optimization of on-chip High Speed Interconnects

As Very Large Scale Integrated (VLSI) technology shrinks to deep sub micron (DSM) geometric (below 0.18 ¿m), interconnect is becoming a limiting factor in determining circuit performance. high speed interconnects suffer from signal integrity effects like crosstalk, and propagation delay thereby degrading the entire system operation. Crosstalk is a significant phenomenon, which arises as a result of coupling of signals between nearby interconnects mainly due to self and mutual inductances and capacitances. This paper, suggests a full wave analysis based on finite difference time domain method (FDTDM) for analyzing an interconnect structure. The variations of interconnect parameters with spacing between conductors are found out and the optimum value, which is suitable for chip designing is obtained by Genetic Algorithm.