By Topic

Modeling and optimization of on-chip High Speed Interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kumar, B.K. ; Kamaraj Coll. of Eng. & Technol., Virudhunagar, India ; Rajeswari, P. ; Kumar, N.S.

As Very Large Scale Integrated (VLSI) technology shrinks to deep sub micron (DSM) geometric (below 0.18 ¿m), interconnect is becoming a limiting factor in determining circuit performance. high speed interconnects suffer from signal integrity effects like crosstalk, and propagation delay thereby degrading the entire system operation. Crosstalk is a significant phenomenon, which arises as a result of coupling of signals between nearby interconnects mainly due to self and mutual inductances and capacitances. This paper, suggests a full wave analysis based on finite difference time domain method (FDTDM) for analyzing an interconnect structure. The variations of interconnect parameters with spacing between conductors are found out and the optimum value, which is suitable for chip designing is obtained by Genetic Algorithm.

Published in:

ElectroMagnetic Interference and Compatibility (INCEMIC), 2006 Proceedings of the 9th International Conference on

Date of Conference:

23-24 Feb. 2006