A high-performance distributed arithmetic processor for the HD video compression

This paper presents a design of high-performance Distributed Arithmetic Processor (DAP) for the efficient implementation of HD video compression algorithms. A Multi-Bit Pipelined Carry-Save DAP (MPCS-DAP) structure have been proposed where two pipelined carry-save accumulators implement the divided look-up table (LUT) DA structure with multi-bit processing in parallel. This structure enables flexible high speed operations at low power consumption based on the pipelined bit-sequential operations. A novel two-bit adder circuitry has been used extensively and HSPICE simulation of the critical path shows that it operates at 200 MHz clock speed at 3.3 volts with 0.8 /spl mu/m double metal CMOS technology. It has also shown that an array of MPCS-DAP can implements 2D DCT/IDCT at 200 M samples per second.