Quasi delay-insensitive bus for fully asynchronous systems

In this paper the design of a dual rail asynchronous system bus is presented. Buses are generally avoided in asynchronous design because it is difficult to meet the isochronic fork assumption on heavily loaded wires. Our bus design avoids this assumption and provides a quasi delay-insensitive solution. The proposed solution makes a system modular and scaleable by guaranteeing that the complexity of the system grows linearly with each module added.