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A Current Reuse Quadrature GPS Receiver in 0.13 \mu m CMOS

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3 Author(s)
Kuang-Wei Cheng ; Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA ; Natarajan, K. ; Allstot, D.J.

A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 3 )