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A low-power, reliable and re-configurable clock recovery circuit for UHF RFID transponders for the EPC Class-1 Generation-2 standard is proposed. Based on a digital frequency-locked loop, the clock recovery circuit uses timing information available in the downlink data, namely, the pulse intervals of the PIE-coded data, to calibrate an oscillator's output frequency to meet the stringent frequency accuracy requirement of the standard. Fabricated in a 0.18-Â¿m standard CMOS technology, the clock recovery circuit provides a calibrated frequency of 2.56 MHz with a frequency deviation within the range from -3.2% to +1.2% over process, supply voltage and temperature variations. The chip has an active area of 0.22 Â¿m2, operates from a supply voltage from 0.75 V to 1.3 V, and consumes less than 2 Â¿W for a 1-V supply.