By Topic

5–10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hossain, M. ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Carusone, A.C.

A low power burst mode receiver architecture is presented which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A low power- and area-efficient clock recovery scheme uses the linear path to injection lock an oscillator. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is verified with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 3 )