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A 0.02-mm ^{2} 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

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2 Author(s)
Yen-Chuan Huang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Tai-Cheng Lee

A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a power consumption of 6.9 mW from a 1.0-V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 3 )

Date of Publication:

March 2010

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