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Assessing merged DRAM/logic technology

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2 Author(s)
Yong-Bin Kim ; Eng. Syst. Lab., Fort Collins, CO, USA ; Chen, T.

This paper describes the impact of the DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuits and the alternative circuit design technology to offset the performance penalty. Three state-of-the-art logic processes (0.5 μm, 0.6 μm, and 0.8 μm) and two state-of-the-art DRAM (64 Mb and 256 Mb) processes have been selected for the study. The simulation results show that the logic circuit performance is degraded by about 22% on the DRAM process including increased interconnect delay due to less interconnect layers available in the DRAM process. The silicon area increased up to 80% depending on the number of nets and components when implementing the logic circuit in the DRAM process

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:4 )

Date of Conference:

12-15 May 1996