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High- \kappa /Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

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19 Author(s)
Khater, M.H. ; IBM T J. Watson Res. Center, Yorktown Heights, NY, USA ; Zhen Zhang ; Jin Cai ; Lavoie, C.
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Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

Published in:

Electron Device Letters, IEEE  (Volume:31 ,  Issue: 4 )

Date of Publication:

April 2010

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