Close category search window
 

Improvement of Poly-Pimple-Induced Device Mismatch on 6T-SRAM at 65-nm CMOS Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Hu, Chan-Yuan ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Chen, Jone F. ; Chen, Shih-Chih ; Shoou-Jinn Chang
more authors

An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

Published in:
Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 4 )

Date of Publication: April 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.