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VLSI architecture design for reconfigurable block size motion estimation

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2 Author(s)
Peng Li ; Department of Electrical and Computer Engineering, University of Minnesota, Duluth 55812, USA ; Hua Tang

This paper presents a VLSI architecture to support full-search motion estimation with reconfigurable block size, which is well needed in video based surveillance applications. Experiment results show that the proposed architecture achieves the flexibility of adjustable block size at the expense of only 5% hardware overhead compared to the traditional design.

Published in:

2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE)

Date of Conference:

9-13 Jan. 2010