By Topic

Activity measures for fast relative power estimation directed numerical transformation for low power DSP synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nguyen, H. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Chatterjee, A.

In this paper, we propose a method for optimizing digital signal processing (DSP) systems for both power and circuit area. The optimization involves application of numerical transformations to the matrices of a linear system. A greedy search algorithm is used, along with fast and efficient activity estimator to synthesize low power systems. The method is applicable to bit-serial, nibble-serial as well as fully word-parallel architectures. In this paper we focus primarily on bit-serial architectures and show that up to 35 percent savings in power and hardware may be obtained

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:4 )

Date of Conference:

12-15 May 1996