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An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules

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3 Author(s)
D. J. Goodwill ; Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA ; K. E. Devenport ; H. S. Hinton

The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm2-sized smart pixel chips are used. This gives a predicted bisection bandwidth of around 1 Tb/s across a 10-in circuit board edge for a full-sized system.

Published in:

IEEE Journal of Selected Topics in Quantum Electronics  (Volume:2 ,  Issue: 1 )