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This paper presents the design of a 10-Gb/s decision feedback equalizer (DFE) for chip-to-chip communications in 90-nm CMOS technology. A fast slicer architecture is proposed that achieves timing constraints without the use of speculation techniques. Removing speculation improves power consumption by 60%. The 5-tap topology was found optimum to compensate for channel losses up to 22 dB. A half-rate architecture is used to enable operation at 10-Gb/s. The DFE system consumes 43 mW from a 1.2 V supply, and occupies an area of 177 Â¿m * 146 Â¿m. Post-layout simulations done using a channel with 22 dB loss at 5 GHz, demonstrate the effectiveness of the DFE equalization.