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Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.