By Topic

A novel framework of Optimizing modular computing architecture for multi objective VLSI designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zhipeng Zeng ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada ; Sedaghat, R. ; Sengupta, A.

For the past few years modular design has become the de facto standard for the development of complex VLSI systems. Most of these modular VLSI system designs are generally multi objective in nature with the requisite to tradeoff between many contradictory parameters like speed, power consumed, cost and hardware area. They are heavily used in low end ASIC's which demand low power consumption and cost with acceptable performance and in high end ASIC's with high performance requirement. This paper presents a novel framework for the optimization of computing architecture based on hierarchy factor method. The determination of this hierarchy factor enables the designer to arrange the various resources of the system in the form of an architecture tree based on the application and the user specifications. The resulting structure would act as a pathway for obtaining the optimal architecture design option for multi objective optimization of the computing architecture used in many VLSI designs. The framework for optimization of computing architecture shown in this paper has been deduced and proved mathematically. The proposed method is capable to determine the most influential resource for a certain performance parameter in the whole system which is deduced by considering the mathematical model of the performance metric. The representation of our approach in the form of architecture tree allows easy automation of the process, useful for many multi objective optimized VLSI designs.

Published in:

Microelectronics (ICM), 2009 International Conference on

Date of Conference:

19-22 Dec. 2009