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A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current

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10 Author(s)
Han Ki Chung ; Nano Syst. Inst.-Nat. Core Res. Center, Seoul Nat. Univ., Seoul, South Korea ; Hoon Jeong ; Yeun Seung Lee ; Jae Young Song
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A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher potential barrier between body and source. To confirm the memory operation of the SGVC cell, we simulated and characterized memory effects such as sensing margin and retention time. According to these results, the SGVC cell can operate as an embedded 1T DRAM having a sufficiently large sensing margin and retention time. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array.

Published in:

Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE

Date of Conference:

15-16 June 2008